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AD9549 데이터시트(PDF) 15 Page - Analog Devices

부품명 AD9549
상세설명  Dual Input Network Clock Generator/Synchronizer
PDF  78 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9549 데이터시트(HTML) 15 Page - Analog Devices

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Preliminary Technical Data
AD9549
Rev. PrA | Page 15 of 78
Plot 7: Additive Phase Noise at HSTL Output Driver. Sysclk = 1 GHz.
(Sysclk PLL enabled and driven with 25MHz Fox Crystal Oscillator.)
Fin=19.44 MHz, Fout=155.52 MHz.
DPLL loop BW=1 kHz.
Plot 8: Additive Phase Noise at CMOS Output Driver.
Sysclk= 500 MHz. Sysclk PLL disabled.
Fin=10.24 MHz, Fout=10.24 MHz.
DPLL loop BW=1 kHz
Plot 9: SFDR vs Fout at Sysclk = 1GHz
with and w/o recon filter.
Fcut = Fout * 1.2
Plot 10: HSTL Output Amplitude vs. Toggle Rate
(100 ohms across differential pair.,)



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