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AD9549 데이터시트(PDF) 12 Page - Analog Devices

부품명 AD9549
상세설명  Dual Input Network Clock Generator/Synchronizer
PDF  78 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9549 데이터시트(HTML) 12 Page - Analog Devices

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AD9549
Preliminary Technical Data
Rev.
PrA | Page 12 of 78
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power Down
ns
Time Req’d to Recover from Power Down
ns
S0-4 Config Setup Time During Reset
ns
Time S0-4 must be present before falling
edge of signal on RESET pin.
S0-4 Config Hold Time During Reset
ns
Time S0-4 must be held after falling edge
of signal on RESET pin.
Reset assert to S0-4 High-Z Time
ns
Time from rising edge of RESET to High Z
on S0-4 configuration pins.
Reset deassert to S0-4 Low-Z time
ns
Time from falling edge of RESET to Low-Z
on S0-4 configuration pins.
CS to SCLK Setup Time
TBD
ns
Period of SCLK
10
ns
TDSU (Serial Data Setup Time)
TBD
ns
TDHD (Serial Data Hold Time)
TBD
ns
TDV (Data Valid Time)
TBD
ns
PROPAGATION DELAY
FDBK to HSTL Output Driver
FDBK to HSTL Output Driver with 2x
Frequency Multiplier Enabled
FDBK to HSTL Output Driver with 2x
Frequency Multiplier Enabled
FDBK to CMOS Output Driver
FDBK through S-Divider to CMOS Output
Driver



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