AD9549 datasheet(10/78 Pages) AD

10 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 10 of 78

DAC OUTPUT CHARACTERISTICS

DCO Frequency range (1st Nyquist zone)

450

MHz

DPLL loop bandwidth sets lower limit

Output Resistance

Ω

single-ended (each pin internally

terminated to AVSS)

Output Capacitance

Full-Scale Output Current

31.7

range depends on DAC RSET resistor

Gain Error

TBD

%FS

Output Offset

0.6

µA

Voltage Compliance Range

AVSS

−0.50

+0.5V

AVSS

+0.50

Outputs not DC shorted to Vss

Wideband SFDR (DC to Nyquist):

SFDR may be improved by activating

Harmonic Spur Suppression (see text)

10MHz Analog Out

TBD

dBc

40MHz Analog Out

TBD

dBc

80MHz Analog Out

TBD

dBc

120MHz Analog Out

TBD

dBc

160MHz Analog Out

TBD

dBc

Narrowband SFDR

10 MHz Analog Out (±1 MHz)

TBD

dBc

40 MHz Analog Out (±1 MHz)

TBD

dBc

80 MHz Analog Out (±1 MHz)

TBD

dBc

120 MHz Analog Out (±1 MHz)

TBD

dBc

160 MHz Analog Out (±1 MHz)

TBD

dBc

DIGITAL PLL

Minimum open-loop bandwidth

0.0001

kHz

dependent on the frequency of REFA/B,

the DAC sample rate, and the P, R, and S

divider values

Maximum open-loop bandwidth

100

kHz

dependent on the frequency of REFA/B,

the DAC sample rate, and the P, R, and S

divider values

Minimum phase margin

degrees

dependent on the frequency of REFA/B,

the DAC sample rate, and the P, R, and S

divider values (not a hard limit but

bounded by 0

°)

Maximum phase margin

degrees

dependent on the frequency of REFA/B,

the DAC sample rate, and the P, R, and S

divider values (not a hard limit but

bounded by 90

°)

PFD input frequency range

~0.008

~24.5

MHz

Feedforward divider ratio

131,070

1,2,..,65,535 or 2,4,..,131,070

Feedback divider ratio

131,070

1,2,..,65,535 or 2,4,..,131,070

LOCK DETECTION

PHASE LOCK DETECTOR

Time Threshold Programming Range

2097

µs

FPFD_Gain=200

Time Threshold Resolution

0.488

FPFD_Gain=200

Lock Time Programming Range

32x10-9

68.7

in power-of-2 steps

Unlock Time Programming Range

64x10-6

16.8

in power-of-2 steps

FREQUENCY LOCK DETECTOR

Normalized Frequency Threshold

Programming Range

0.0021

FPFD_Gain=200; normalized to (fREF/R)2;

see text for details

Normalized Frequency Threshold

5x10-13

FPFD_Gain=200; normalized to (fREF/R)2;

AD9549 데이터시트(PDF) 10 Page - Analog Devices

AD9549 데이터시트(HTML) 10 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

데이터시트 다운로드

링크 URL