AD9549 datasheet(75/78 Pages) AD

75 / 78 page

Preliminary Technical Data

AD9549

Rev. PrA | Page 75 of 78

0319 – 031C; Frequency Lock

[31:0] Frequency Lock Threshold: See “Frequency Lock Detection” on Page 32.

031D; Frequency Lock (continued)

[7:5] Frequency Unlock Watchdog Timer: See “Frequency Lock Detection” on Page 32.

[4:0] Frequency Lock Watchdog Timer: See “Frequency Lock Detection” on Page 32.

031E – 031F; Loss of Reference

[15:0] RefA LOR Divider: See “Loss of Reference” on Page 33.

0320 – 0321; Loss of Reference (continued)

[15:0] RefB LOR Divider: See “Loss of Reference” on Page 33.

0322 – 0323; Reference Out Of Limits (OOL)

[15:0] RefA OOL Divider: See “Reference Frequency Monitor” on Page 33.

0324 – 0327; Reference OOL (continued)

[31:0] RefA OOL Upper Limit: See “Reference Frequency Monitor” on Page 33.

0328 – 032B; Reference OOL (continued)

[31:0] RefA OOL Lower Limit: See “Reference Frequency Monitor” on Page 33.

032C – 032D; Reference OOL (continued)

[15:0] RefB OOL Divider: See “Reference Frequency Monitor” on Page 33.

032E – 0331; Reference OOL (continued)

[31:0] RefB OOL Upper Limit: See “Reference Frequency Monitor” on Page 33.

0332 – 0335; Reference OOL (continued)

[31:0] RefB OOL Lower Limit: See “Reference Frequency Monitor” on Page 33.

Calibration (User Accessible Trim)

0400 – 0401; K Divider

[15:0] K Divider: The K divider alters precision of frequency estimator circuit. See “Frequency Estimator” on Page 47.

0402; CPFD Gain

[2:0] CPFD Gain Scale: This register is the coarse phase frequency power of 2 multiplier (PDS). See “Phase Detector” on

Page 27. Note that the correct value for this register will be calculated by filter design software provided with the evaluation

board.

0403; CPFD Gain (continued)

[5:0] CPFD Gain: This register is the coarse phase frequency linear multiplier (PDG). See “Phase Detector” on Page 27. Note

that the correct value for this register will be calculated by filter design software provided with the evaluation board.

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