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IA88C00-PDW48I-R 데이터시트(PDF) 24 Page - InnovASIC, Inc

부품명 IA88C00-PDW48I-R
상세설명  Microcontroller
PDF  80 Pages
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제조업체  INNOVASIC [InnovASIC, Inc]
홈페이지  http://www.innovasic.com
Logo INNOVASIC - InnovASIC, Inc

IA88C00-PDW48I-R 데이터시트(HTML) 24 Page - InnovASIC, Inc

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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright © 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 24 of 80
1.888.824.4184
Figure 15. Instruction Pointer High (IPH), R218
Bit
7
6
5
4
3
2
1
0
IP15
IP14
IP13
IP12
IP11
IP10
IP9
IPO8
Initial Value
?
?
?
?
?
?
?
?
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
A special register called the Instruction Pointer (IP) provides hardware support for threaded-code
languages. It consists of register-pair R218-R219 and contains memory addresses. The MSB is R218.
Threaded-code languages deal with an imaginary higher-level machine within the existing hardware
machine. The IP acts like the PC for that machine. The command NEXT passes control to or from the
hardware machine to the imaginary machine. And the commands ENTER and EXIT are imaginary
machine equivalents of real machine CALLS and RETURNS.
If the commands NEXT, ENTER and EXIT are not used, the IP can be used by the fast interrupt
processing, as described in the interrupts section.
Figure 16. Instruction Pointer Low (IPL), R219
Bit
7
6
5
4
3
2
1
0
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
Initial Value
?
?
?
?
?
?
?
?
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
A special register called the Instruction Pointer (IP) provides hardware support for threaded-code
languages. This register consists of register pair R218-R219 and contains memory addresses. The MSB is
R218. Threaded-code languages deal with an imaginary higher-level machine within the existing
hardware machine. The IP acts like the PC for that machine. The command NEXT passes control to or
from the hardware machine to the imaginary machine. And the commands ENTER and EXIT are
imaginary machine equivalents of real machine CALLS and RETURNS.
The IP can be used by the fast interrupt processing, as described in the interrupts section, if the commands
NEXT, ENTER and EXIT are not used.
Figure 17. Interrupt Mask (IRM), R221
Bit
7
6
5
4
3
2
1
0
Level 7
Level 7
Level 7
Level 7
Level 7
Level 7
Level 7
Level 7
Initial Value
?
?
?
?
?
?
?
?
Read/Write
R
R
R
R
R
R
R
R



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