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IA88C00-PDW48I-R 데이터시트(PDF) 60 Page - InnovASIC, Inc |
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IA88C00-PDW48I-R 데이터시트(HTML) 60 Page - InnovASIC, Inc |
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60 / 80 page ![]() IA88C00 Data Sheet Microcontroller As of Production Version -01 Copyright © 2005 ENG21 1 030617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 60 of 80 1.888.824.4184 Halt Mode When the IA88C00 execute the Wait for Interrupt (WFI) instruction and bit 3 of R223 (Halt Mode register) is cleared, the processor enters HALT mode. The internal CPU clock is disabled, however, the oscillator remains active. Use of the UART, timers and DMA remains under user control. The Halt mode is exited via an interrupt or DMA request. The programming model for Halt Mode is detailed in R223 (Halt Mode register) |
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