IA88C00-PDW48I-R datasheet(13/80 Pages) INNOVASIC

13 / 80 page

IA88C00

Data Sheet

Microcontroller

As of Production Version -01

ENG 21 0 050519-00

www.Innovasic

Innovasic.com

Innovasic Semiconductor

Page 13 of 80

1.888.824.4184

Architecture

IA88C00 maintains program model compatibility with the Super8 architecture, including 268 general

purpose registers and 57 registers for control and mode functions.

The instruction set, is also fully binary compatible supporting all instructions, including multiply and

divide instructions and provisions for BCD operations.

The peripheral set maintains register/ program model compatibility. Robust serial communications are

provided by an on-board UART. Counter/timers are provided for time-sensitive/control loop

applications. A watchdog timer is provided for processor sanity.

Pin Descriptions

/AS Address Strobe

(output, active Low)

The rising edge of this output indicates that address, R/W, and DM (when

appropriate) are valid.

/DS Data Strobe

(output, active Low

The leading edge of this signal indicates that data is valid during a write cycle.

The trailing edge of this signal is used to latch data into the IA88C00 during a

read cycle.

P00-P07, P10-P17,

P20-P27, P30-P37,

P40-P47, Port I/O

Lines (input/output)

Input/Output Ports configured under program control. Specific functions include:

Port 1 serves as the multiplexed address/data port. It serves as the data bus

de-multiplexed mode, and Port 0 pins can be used as additional address

lines or general purpose I/O.

Ports 2 and 3 provide support for interrupts, the UART and the timers.

Alternatively, they can be programmed as general purpose I/O.

Port 4 is used for general I/O or as the lower address byte in de-mux mode.

/RESET (input,

active Low)

Reset input. Reset vector is address 0020H.

R/W Read/Write

(output)

When high, the current bus operation is a read. When low, the current bus

operation is a write.

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