M25P40-VMP6TGSLASHX datasheet(13/53 Pages) STMICROELECTRONICS

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M25P40

Operating features

13/53

4.5

Status Register

The Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. For a detailed description of the Status Register bits,

see Section 6.4: Read Status Register (RDSR).

4.6

Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. To help combat this, the

M25P40 features the following data protection mechanisms:

●

Power On Reset and an internal timer (tPUW) can provide protection against inadvertent

changes while the power supply is outside the operating specification.

●

Program, Erase and Write Status Register instructions are checked that they consist of

a number of clock pulses that is a multiple of eight, before they are accepted for

execution.

●

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–Power-up

–

Write Disable (WRDI) instruction completion

–

Write Status Register (WRSR) instruction completion

–

Page Program (PP) instruction completion

–

Sector Erase (SE) instruction completion

–

Bulk Erase (BE) instruction completion

●

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as

read-only. This is the Software Protected Mode (SPM).

●

The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status

Mode (HPM).

●

In addition to the low power consumption feature, the Deep Power-down mode offers

extra software protection from inadvertent Write, Program and Erase instructions, as all

instructions are ignored except one particular instruction (the Release from Deep

Power-down instruction).

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