M25P40-VMP6TGSLASHX datasheet(18/53 Pages) STMICROELECTRONICS

18 / 53 page

Instructions

M25P40

18/53

Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select

(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most

significant bit first, on Serial Data input (D), each bit being latched on the rising edges of

Serial Clock (C).

The instruction set is listed in Table 4.

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

Chip Select (S) must be driven High after the last bit of the instruction sequence has been

shifted in.

In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),

Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Power-

down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence

is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the

data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status

instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the

instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when

the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of

eight.

All attempts to access the memory array during a Write Status Register cycle, Program

cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program

cycle or Erase cycle continues unaffected.

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