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M25P40-VMP6TG/X 데이터시트(PDF) 44 Page - STMicroelectronics

부품명 M25P40-VMP6TG/X
상세설명  4 Mbit, low voltage, serial Flash memory with 50 MHz SPI bus interface
PDF  53 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M25P40-VMP6TG/X 데이터시트(HTML) 44 Page - STMicroelectronics

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DC and ac parameters
M25P40
44/53
Table 21.
AC characteristics (40 MHz operation, device grade 6, VCC min = 2.3 V)
Extended VCC range available only in products with Process Technology code X
(1)
Test conditions specified in Table 10 and Table 17
1.
Details of how to find the date of marking are given in Application Note, AN1995.
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
fC
fC
Clock frequency for the following
instructions: FAST_READ, PP, SE, BE, DP,
RES, WREN, RDID, WRDI, RDSR, WRSR
D.C.
40
MHz
fR
Clock frequency for READ instructions
D.C.
25
MHz
tCH
(2)
2.
tCH + tCL must be greater than or equal to 1/ fC
tCLH
Clock High time
11
ns
tCL
(2)
tCLL
Clock Low time
11
ns
tCLCH
(3)
3.
Value guaranteed by characterization, not 100% tested in production.
Clock Rise time(4) (peak to peak)
4.
Expressed as a slew-rate.
0.1
V/ns
tCHCL
(3)
Clock Fall time(4) (peak to peak)
0.1
V/ns
tSLCH
tCSS
S Active Setup time (relative to C)
5
ns
tCHSL
S Not Active Hold time (relative to C)
5
ns
tDVCH
tDSU
Data In Setup time
2
ns
tCHDX
tDH
Data In Hold time
5
ns
tCHSH
S Active Hold time (relative to C)
5
ns
tSHCH
S Not Active Setup time (relative to C)
5
ns
tSHSL
tCSH
S Deselect time
100
ns
tSHQZ
(3)
tDIS
Output Disable time
8
ns
tCLQV
tV
Clock Low to Output Valid
8
ns
tCLQX
tHO
Output Hold time
0
ns
tHLCH
HOLD Setup time (relative to C)
5
ns
tCHHH
HOLD Hold time (relative to C)
5
ns
tHHCH
HOLD Setup time (relative to C)
5
ns
tCHHL
HOLD Hold time (relative to C)
5
ns
tHHQX
(3)
tLZ
HOLD to Output Low-Z
8
ns
tHLQZ
(3)
tHZ
HOLD to Output High-Z
8
ns
tWHSL
(5)
5.
Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Write Protect Setup time
20
ns
tSHWL
(5)
Write Protect Hold time
100
ns
tDP
(3)
S High to Deep Power-down mode
3
µs
tRES1
(3)
S High to Standby Power mode without
Electronic Signature Read
30
µs
tRES2
(3)
S High to Standby Power mode with
Electronic Signature Read
30
µs



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