M25P40-VMP6TGSLASHX datasheet(14/53 Pages) STMICROELECTRONICS

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Operating features

M25P40

14/53

4.7

Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence. However, taking this signal Low does not terminate any

Write Status Register, Program or Erase cycle that is currently in progress.

To enter the Hold condition, the device must be selected, with Chip Select (S) Low.

The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low (as shown in Figure 5).

The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition

starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes

Low. (This is shown in Figure 5).

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration

of the Hold condition. This is to ensure that the state of the internal logic remains unchanged

from the moment of entering the Hold condition.

If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of

resetting the internal logic of the device. To restart communication with the device, it is

necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents

the device from going back to the Hold condition.

Table 2.

Protected area sizes

Status Register

content

Memory content

BP2

bit

BP1

bit

BP0

bit

Protected area

Unprotected area

none

All sectors(1) (eight sectors: 0 to 7)

The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are

Upper eighth (Sector 7)

Lower seven-eighths (seven sectors: 0 to

Upper quarter (two sectors: 6 and 7) Lower three-quarters (six sectors: 0 to 5)

Upper half (four sectors: 4 to 7)

Lower half (four sectors: 0 to 3)

All sectors (eight sectors: 0 to 7)

none

All sectors (eight sectors: 0 to 7)

none

All sectors (eight sectors: 0 to 7)

none

All sectors (eight sectors: 0 to 7)

none

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