UPSD3422 datasheet(219/293 Pages) STMICROELECTRONICS

219 / 293 page

uPSD34xx

PSD module

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28.5.28

Output macrocell

The GPLD has 16 OMCs. Architecture of one individual OMC is shown in Figure 77. OMCs

can be used for internal node feedback (buried registers to build shift registers, etc.), or their

outputs may be routed to external port pins. The user can choose any mixture of OMCs

used for buried functions and OMCs used to drive port pins.

Referring to Figure 77, for each OMC there are native product terms available from the

AND-OR Array to form logic, and also borrowed product terms are available (if unused) from

other OMCs. The polarity of the final product term output is controlled by the XOR gate.

Each OMC can implement sequential logic using the flip-flop element, or combinatorial logic

when bypassing the flip-flop as selected by the output multiplexer. An OMC output can drive

a port pin through the OMC Allocator, it can also drive the 8032 data bus, and also it can

drive a feedback path to the AND-OR Array inputs, all at the same time.

The flip-flop in each OMC can be synthesized as a D, T, JK, or SR type in PSDsoft Express.

OMC flip-flops are specified using PSDsoft Express in the “User Defined Nodes” section of

the Design Assistant. Each flip-flop’s clock, preset, and clear inputs may be driven

individually from a product term of the AND-OR Array, defined by equations in PSDsoft

Express for signals *. c, *.pr, and *.re respectively. The preset and clear inputs on the flip-

flops are level activated, active-high logic signals. The clock inputs on the flip-flops are

rising-edge logic signals.

Optionally, the signal CLKIN (pin PD1) can be used for a common clock source to all OMC

flip-flops. Each flip-flop is clocked on the rising edge. A common clock is specified in

PSDsoft Express by assigning the function “Common Clock Input” for pin PD1 in the Pin

Definition section, and then choosing the signal CLKIN when specifying the clock input (*.c)

for individual flip-flops in the “User Defined Nodes” section.

UPSD3422 데이터시트(PDF) 219 Page - STMicroelectronics