UPSD3422 datasheet(217/293 Pages) STMICROELECTRONICS

217 / 293 page

uPSD34xx

PSD module

217/293

Figure 75.

DPLD Logic Array

28.5.27

General PLD (GPLD)

The GPLD is used to create general system logic. Figure 74 on page 215 shows the

architecture of the entire GPLD, and Figure 76 on page 218 shows the relationship between

one OMC, one IMC, and one I/O port pin, which is representative of pins on Ports A, B, and

C. It is important to understand how these elements work together. A more detailed

description will follow for the three major blocks (OMC, IMC, I/O Port) shown in Figure 76.

Figure 76 also shows which csiop registers to access for various PLD and I/O functions.

The GPLD contains:

●

16 Output Macrocells (OMC)

●

20 Input Macrocells (IMC)

●

OMC Allocator

●

Product Term Allocator inside each OMC

●

AND-OR Array capable of generating up to 137 product terms

●

Three I/O Ports, A, B, and C

FS0

FS1

FS7

FS6

FS5

FS4

FS3

FS2

MAIN

FLASH

MEMORY

SECTOR

SELECTS

CSBOOT0

CSBOOT3

CSBOOT2

CSBOOT1

SECONDARY

FLASH

MEMORY

SECTOR

SELECTS

RS0

SRAM

SELECT

CSIOP

I/O & CONTROL

REGISTERS

SELECT

ECS0

ECS1

EXTERNAL

CHIP-

SELECTS

(PORT D)

PSEL0

PSEL1

PERIPHERAL

I/O MODE

RANGE

SELECTS

8032 ADDRESS (A0 - A15)

POWER-DOWN INDICATOR (PDN)

PIN INPUT PORTS A, B, C (IMCs)

PIN INPUT PORT D

OMC FEEDBACK (MCELLAB.FB0-7)

PAGE REGISTER (PGR0 - PGR7)

OMC FEEDBACK (MCELLBC.FB0-7)

PLD INPUT BUS

NUMBER OF

PRODUCT TERMS

AI06601A

PSM MODULE RESET (RST)

FLASH MEM PROG STATUS (RDYBSY)

8032 CNTL (RD, WR, PSEN, ALE)

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