UPSD3422 datasheet(243/293 Pages) STMICROELECTRONICS

243 / 293 page

uPSD34xx

PSD module

243/293

of unused input pins from drawing excessive current.

The csiop PMMR register definitions are shown in Table 144 through Table 146 on

page 244.

Table 144.

Power management mode register PMMR0 (address = csiop + offset B0h)

Note:

All the bits of this register are cleared to zero following Power-up. Subsequent Reset (RST)

pulses do not clear the registers.

Note:

Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD

logic equation.

Bit 0

Not used, and should be set to zero.

Bit 1

APD Enable

Automatic Power Down (APD) counter is disabled.

APD counter is enabled

Bit 2

Not used, and should be set to zero.

Bit 3

PLD Turbo

Disable

0 =

PLD Turbo mode is on

1 =

off

PLD Turbo mode is off, saving power.

Bit 4

Blocking Bit,

CLKIN to

PLDs(1)

0 =

CLKIN (pin PD1) to the PLD Input Bus is not blocked. Every transition of

CLKIN powers-up the PLDs.

1 =

off

CLKIN input to PLD Input Bus is blocked, saving power. But CLKIN still

goes to APD counter.

Bit 5

Blocking Bit,

CLKIN to

OMCs

Only(1)

0 =

CLKIN input is not blocked from reaching all OMCs’ common clock

inputs.

1 =

off

CLKIN input to common clock of all OMCs is blocked, saving power. But

CLKIN still goes to APD counter and all PLD logic besides the common

clock input on OMCs.

Bit 6

Not used, and should be set to zero.

Bit 7

Not used, and should be set to zero.

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