UPSD3422 datasheet(255/293 Pages) STMICROELECTRONICS

255 / 293 page

uPSD34xx

PSD module

255/293

TSTAT and TERR are functional only when JTAG ISP operations are occurring, which

means they are non-functional during JTAG debugging of the 8032 on the MCU Module.

Programming times vary depending on the number of locations to be programmed and the

JTAG programming equipment, but typical JTAG ISP programming times are 10 to 25

seconds using 6-pin JTAG. The signals TSTAT and TERR are not included in the IEEE

1149.1 specification.

Figure 93 on page 255 shows recommended connections on a circuit board to a JTAG

program/test tool using 6-pin JTAG. It is required to connect the RST output signal from the

JTAG program/test equipment to the RESET_IN input on the uPSD34xx. The RST signal is

driven by the equipment with an Open Drain driver, allowing other sources (like a push

button) to drive RESET_IN without conflict.

Note:

The recommended pull-up resistors and decoupling capacitor are illustrated in Figure 93.

Figure 93.

Recommended 6-pin JTAG connections

Note:

For 5V uPSD34xx devices, pull-up resistors and VCC pin on the JTAG connector should be

connected to 5V system VDD.

For 3.3V uPSD34xx devices, pull-up resistors and VCC pin on the JTAG connector should be

connected to 3.3V system VCC.

This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than

one source to activate RESET_IN.

TMS - PC0

TCK - PC1

SRAM STBY or I/O - PC2

TSTAT - PC3

TERR - PC4

TDI - PC5

TDO - PC6

GENERAL I/O - PC7

JTAG

CONN.

100k typical

TMS

TCK

TDI

TERR

TSTAT

TDO

GENERAL I/O

SIGNALS

GND

VCC

(1,2)

RST

(3)

uPSD34xx

0.01

µF

CIRCUIT

BOARD

JTAG

Programming

or Test

Equipment

Connects Here

10k

PUSH BUTTON

or ANY OTHER

RESET SOURCE

DEBUG

OPTIONAL

TEST POINT

100k

RESETIN

AI10458

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