TMP88CU74F datasheet(7/132 Pages) TOSHIBA

7 / 132 page

TMP88CU74

2003-02-17

88CU74-7

Operational Description

CPU Core Functions

The CPU core consists of a CPU, a system clock controller, an interrupt controller, and a

watchdog timer.

This section provides a description of the CPU core, the program memory (ROM), the data

memory (RAM), and the reset circuit.

1.1

Memory Address Map

TLCS-870/X Series, the memory is organized 4 address spaces (ROM, RAM, SFR, and DBR).

Figure 1.1.1 shows the memory address maps of the TMP88CU74. It uses a memory mapped

I/O system, and all I/O registers are mapped in the SFR/DBR address spaces. There are 16

banks of general-purpose registers.

Figure 1.1.1 Memory Address Maps

1.2

Program Memory (ROM)

The TMP88CU74 has a 96 Kbytes (addresses 04000H to 1BFFFH) and 256 bytes (addresses

FFF00H to FFFFFH) of program memory (mask programmed ROM). Figure 1.1.1 shown in

Memory address maps.

Addresses FFF00H to FFFFFH in the program memory can also be used for special purposes.

64 bytes

00000H

0003F

1920 bytes

SFR

RAM

128 bytes

00040

000BF

000C0

0083F

(8 registers

× 16 banks)

ROM: Read Only Memory includes:

Program memory

Vector table

RAM: Random Access Memory includes:

Data memory

Stack

General-purpose register banks

SFR: Special Function Register includes:

I/O ports

Peripheral control registers

Peripheral status registers

System control registers

Interrupt control registers

Program Status Word

DBR: Data Buffer Register includes:

SIO data buffer

VFT display data buffer

128 bytes

00F80

00FFF

04000

1BFFF

98304

bytes

64 bytes

FFF00

FFF3F

FFF40

FFF7F

FFF80

FFFBF

FFFC0

FFFFF

DBR

ROM

TMP88CU74

Vector table for interrupts/

Reset (16 vectors)

Vector table for vector call

instructions (16 vectors)

2007-10-19

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