TMP88CU74F datasheet(85/132 Pages) TOSHIBA

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88CU74-85

TMP88CU74

2007-10-19

(1) Acknowledge mode specification

Set the ACK (bit 4 in SBICR1) to

“1” for operation in the acknowledge mode. The

TMP88CU74 generates an additional clock pulse for an acknowledge signal when

operating in the master mode. In the transmitter mode during the clock pulse cycle, the

SDA pin is released in order to receive the acknowledge signal from the receiver. In the

receiver mode during the clock pulse cycle, the SDA pin is set to the low level in order

to generate the acknowledge signal.

Reset the ACK for operation in the non-acknowledge mode. The TMP88CU74 does

not generate a clock pulse for the acknowledge signal when operating in the master

mode.

In the acknowledge mode, the TMP88CU74 counts a clock pulse for the acknowledge

signal when operating in the slave mode. During the clock pulse, when the received

slave address is the same as the value set at the I2CAR or when a GENERAL CALL is

received, the SDA pin is set to the low level in order to generate the acknowledge

signal.

In the transmitter mode during the clock pulse cycle after matching the slave

addresses or receiving a GENERAL CALL, the SDA pin is released in order to receive

the acknowledge signal from the receiver. In the receiver mode during the clock pulse

cycle, the SDA pin is set to the low level in order to generate the acknowledge signal.

In non-acknowledge mode, the TMP88CU74 does not count a clock pulse for the

acknowledge signal when operating in the slave mode.

(2) Number of transfer bits

The BC (bits 7 to 5 in SBICR1) is used to select a number of bits for transmitting and

receiving data.

Since the BC is cleared to

“000” as a start condition, a slave address and direction bit

transmissions are always executed in 8 bits. Other than these, the BC retains a

specified value.

(3) Serial clock

a. Clock source

The SCK (bits 2 to 0 in SBICR1) is used to select a maximum transfer frequency output

from the SCL pin in the master mode. Set a communication baud rate that meets the I2C

bus specification, such as the shortest pulse width of tLOW, based on the equations shown

below.

In both master mode and slave mode, a pulse width of at least 4 machine cycles is

required for both high and low levels.

Figure 2.10.5 Clock Source

1/fscl

tLOW

tHIGH

tLOW = 2 /fc

tHIGH = 2 /fc + 8/fc

fscl = 1/(tLOW + tHIGH)

fc:

(Bits 2 to 0 in the SBICR1)

000

001

010

011

100

101

110

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