TMP88CU74F datasheet(28/132 Pages) TOSHIBA

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TMP88CU74

2003-02-17

88CU74-28

(2) Interrupt enable register (EIR)

The interrupt enable register (EIR) enables and disables the acceptance of interrupts,

except for the pseudo non-maskable interrupts (software and watchdog timer interrupts).

Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR;

however, the pseudo non-maskable interrupts cannot be nested more than once at the same

time. For example, the watchdog timer interrupt is not accepted during the software

interrupt service.

The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt

enable flags (EF). This register is assigned to addresses 0003AH and 0003BH in the SFR,

and can be read and written by an instruction (including read-modify-write instructions

such as bit manipulation instructions).

Interrupt master enable flag (IMF)

The interrupt master enable flag (IMF) enables and disables the acceptance of all

interrupts, except for pseudo non-maskable interrupts. Clearing this flag to “0”

disables the acceptance of all maskable interrupts. Setting to “1” enables the

acceptance of interrupts.

When an interrupt is accepted, this flag is cleared to “0” to temporarily disable the

acceptance of maskable interrupts. After execution of the interrupt service program,

this flag is set to “1” by the maskable interrupt return instruction [RETI] to again

enable the acceptance of interrupts. If an interrupt request has already been occurred,

interrupt service starts immediately after execution of the [RETI] instruction.

Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this case,

the IMF is set to “1” only when pseudo non-maskable interrupt service is started with

interrupt acceptance enabled (IMF = 1). Note that the IMF remains “0” when cleared

by the interrupt service program.

The IMF is assigned to bit 0 at address 0003AH in the SFR, and can be read and

written by an instruction. The IMF is normally set and cleared by the [EI] and [DI]

instructions, and the IMF is initialized to “0” during reset.

Individual interrupt enable flags (EF15 to EF4)

These flags enable and disable the acceptance of individual maskable interrupts,

except for an external interrupt 0. Setting the corresponding bit of an individual

interrupt enable flag to “1” enables acceptance of an interrupt, setting the bit to “0”

disables acceptance.

Example 1: Sets EF for individual interrupt enable, and sets IMF to “1”.

LDW

(EIRL), 1110100010100001B

;

EF15 to EF13, EF11, EF7, EF5,

IMF

← 1

Example 2: Sets an individual interrupt enable flag to “1”.

SET

(EIRH).4

;

EF12

← 1

2007-10-19

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