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TMP86CS49FG 데이터시트(PDF) 119 Page - Toshiba Semiconductor

부품명 TMP86CS49FG
상세설명  8 Bit Microcontroller
PDF  252 Pages
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP86CS49FG 데이터시트(HTML) 119 Page - Toshiba Semiconductor

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Page 105
TMP86CS49FG
10.3 Function
The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8-
bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16-
bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter,
16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
10.3.1 8-Bit Timer Mode (TC3 and 4)
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is
cleared. After being cleared, the up-counter restarts counting.
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation
may not be obtained.
Note 3: j = 3, 4
Table 10-4 Source Clock for TimerCounter 3, 4 (Internal Clock)
Source Clock
Resolution
Maximum Time Setting
NORMAL1/2, IDLE1/2 mode
SLOW1/2,
SLEEP1/2
mode
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
DV7CK = 0
DV7CK = 1
fc/211 [Hz]
fs/23 [Hz]
fs/23 [Hz]
128
µs244.14 µs
32.6 ms
62.3 ms
fc/27
fc/27
–8
µs
2.0 ms
fc/25
fc/25
–2
µs
510
µs–
fc/23
fc/23
500 ns
127.5
µs–
Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80
µs later
(TimerCounter4, fc = 16.0 MHz)
LD
(TTREG4), 0AH
: Sets the timer register (80
µs
÷27/fc = 0AH).
DI
SET
(EIRH). 1
: Enables INTTC4 interrupt.
EI
LD
(TC4CR), 00010000B
: Sets the operating clock to fc/27, and 8-bit timer mode.
LD
(TC4CR), 00011000B
: Starts TC4.



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