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LAN9252/ML 데이터시트(PDF) 268 Page - Microchip Technology

부품명 LAN9252/ML
상세설명  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML 데이터시트(HTML) 268 Page - Microchip Technology

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LAN9252
DS00001909A-page 268
 2015 Microchip Technology Inc.
Note 34:
Write access depends upon the assignment of the MI interface (ECAT/PDI).
Note:
Port 3 is not used.
12.14.59 FMMU[2:0] REGISTERS
The device includes 3 FMMUs. Each FMMU is described in 16 Bytes, starting at 0600h. Table 12-16 details the base
address for each FMMU. The subsequent FMMU registers will be referenced as an offset from these various base
addresses. The variable “x” is used in the following descriptions to represent FMMUs 0 through 2.
12.14.59.1 FMMUx Logical Start Address Register
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
2
Port x Link Status Error
0:
No Error
1:
Link Error, Link Inhibited
RO
RO
0b
1
Port x Link Status
(100 Mbit/s, Full-Duplex, Auto-negotiation)
0:
No Link
1:
Link Detected
RO
RO
0b
0
Port x Physical Link
(PHY Status Register 1.2)
0:
No Physical Link
1:
Physical Link Detected
RO
RO
0b
TABLE 12-16: FMMU X BASE ADDRESSES
FMMU
Base Address
0
0600h
1
0610h
2
0620h
Offset:
FMMUx Base Address +0h-3h
Size:
32 bits
Bits
Description
ECAT
Type
PDI
Type
Default
31:0
Logical Start Address
Logical start address within the EtherCAT address space.
R/W
RO
00000000h
Bits
Description
ECAT
Type
PDI
Type
Default



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