D950-CORE datasheet(69/89 Pages) STMICROELECTRONICS

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D950-Core

On the external side:

EA0/EA15 (external address bus) and ED0/ED15 (external data bus) with their associ-

ated control signals

EXRD/DS (external X-bus read (*) or data strobe (**) / output)

EXWR/RD (external X-bus write (*) or read/write (**) / output)

EYRD/DS (external Y-bus read (*) or data strobe (**) / output)

EYWR/RD (external Y-bus write (*) or read/write (**) / output)

EIRD/DS (external I-bus read (*) or data strobe (**) / output)

EIWR/RD (external I-bus write (*) or read/write (**) / output)

DEID (direct access external I memory enable)

DEXD (direct access external X memory enable)

DEYD (direct access external Y memory enable)

Note:

(*) INTEL type interface

(**) MOTOROLA type interface

RESET (reset / input)

DTACKin (data transfer acknowledge/input)

7.2.3 Operation

The BSU recognizes a bus cycle when IBS, XBS or YBS is activated. It decodes the address

value to determine if an external memory access is requested on the I, X or Y-bus and

generates the appropriate signals on the external bus side. The BSU can also generate the

DTACK signal only, depending on a control register bit value.

If more than one external memory access is attempted at one instruction cycle, they are

serviced sequentially in the following order: I-bus, X-bus, Y-bus.

If one or more external memory accesses are attempted in read mode, the corresponding

internal memory space can be disabled using IID (for I-bus), IXD (for X-bus) or IYD (for Y-bus),

assigned low until the end of the instruction cycle.

Each external access requires one basic instruction clock cycle (two CLKIN cycles), extended

by, at least, one wait-state (one BSU_CLK cycle). The number of wait-states can be extended,

either by software with the BSU control registers (see Section 7.2.4), or by hardware with the

DTACKin signal.

During each external memory access and according to the selected interface (INTEL or

MOTOROLA) and bus (X, Y or I), the corresponding external control signals are assigned low

and synchronized to the rising edge of BSU_CLK.

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