D950-CORE datasheet(71/89 Pages) STMICROELECTRONICS

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D950-Core

XER0/1: X-memory space control registers

After reset, XER0/1 default values are 0x83EF/0x83FF

IM:

Intel/ Motorola

0: Motorola type for memories

1: Intel type for memories (def.)

EN_X:

Enable for X-space data exchanges

XA15 / XA10 X-memory space map for boundary on-chip or off-chip

W3 / W0:

Wait state count (1 to 16) for off-chip access (X-memory space)

YER0/1: Y-memory space control registers

After reset, YER0/1 default values are 0x83EF/0x83FF

IM:

Intel / Motorola

0: Motorola type for memories

1: Intel type for memories (def.)

EN_Y:

Enable for Y-space data exchanges

YA15 / YA10: Y-memory space Map for boundary on-chip or off-chip

W3 / W0:

Wait state count (1 to 16) for off-chip access (Y-memory space)

IER0/1: Instruction memory control registers

After reset, IER0/1 default values are 0x83EF/0x83FF

IM:

Intel / Motorola

0: Motorola type for memories

1: Intel type for memories (def.)

EN_I:

Enable for I-space data exchanges

IA15 / IA10:

I-memory space Map for boundary on-chip or off-chip

W3 / W0:

Wait state count (1 to 16) for off-chip access (I-memory space)

9876543210

EN_X

----

XA15

XA14

XA13

XA12

XA11

XA10

9876543210

EN_Y

----

YA15

YA14

YA13

YA12

YA11

YA10

9876543210

EN_I

----

IA15

IA14

IA13

IA12

IA11

IA10

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