STM32WB09XE datasheet(9/73 Pages) STMICROELECTRONICS

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•

Flash memory erase operations: page erase or mass erase

•

Page write protect mechanism: 4 variable-size memory segments

3.4.2

Embedded SRAM

The STM3WB09xE has a total of 64 Kbytes of embedded SRAM, split into four banks as shown in the following

table:

Table 2. SRAM overview

SRAM bank

Size

Address

Retained in Deepstop

SRAM0

16 Kbytes

0x2000 0000

Always

SRAM1

16 Kbytes

0x2000 4000

Programmable by the user

SRAM2

16 Kbytes

0x2000 8000

Programmable by the user

SRAM3

16 Kbytes

0x2000 C000

Programmable by the user

3.4.3

Embedded ROM

The STM3WB09xE has a total of 7 Kbytes of embedded ROM. This area is ST reserved and contains:

•

The UART bootloader from which the CPU boots after each reset (first 6 Kbytes of ROM memory)

•

Some ST reserved values including the ADC trimming values (the last 1 Kbytes of ROM memory)

3.4.4

Embedded OTP

The one-time-programmable (OTP) is a memory of 1 Kbytes dedicated for user data. The OTP data cannot be

erased.

The user can protect the OTP data area by writing the last word at address 0x1000 1BFC and by performing a

system reset. This operation freezes the OTP memory from further unwanted write operations.

3.5

Security and safety

The STM3WB09xE contains many security blocks for the Bluetooth® LE and the host application.

It includes:

•

Flash read/write protections over accidental and intentional actions

•

As protection against potential hacker attacks, the SWD access can be disabled

•

Secure bootloader

•

Customer storage of the Bluetooth® LE keys

•

True random number generator (TRNG) supporting NIST special publication 800-90B

•

Private key accelerator (PKA) including:

–

Modular arithmetic including exponentiation with maximum modulo size of 3136 bits

–

Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with

maximum modulo size of 521 bits

–

Security level allowing constant time operations

•

Cyclic redundancy check calculation unit (CRC)

3.6

Boot modes

Following CPU boot, the application software can modify the memory map at address 0x0000 0000. This

modification is performed by programming the REMAP bit in the flash controller.

The following memory can be remapped:

•

Main flash memory

•

SRAM0 memory

STM32WB09xE

Functional overview

DS14210 - Rev 6

page 9/73

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