STM32WB09XE datasheet(18/73 Pages) STMICROELECTRONICS

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Flash controller: in parallel with the system clock, the flash controller uses an always 16 MHz clock to

generate specific delays required by the flash memory during programming and erase operations for

example

•

PKA: in parallel with the system clock, the PKA uses the system clock frequency

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Radio: it does not directly use the system clock for its APB/AHB interfaces, but the system clock with a

potential divider (1 or 2 or 4). In parallel, the radio uses an always 16 MHz and an always 32 MHz for

modulator, demodulator and to have a fixed reference clock to manage specific delays

•

ADC: in parallel with the system clock, ADC uses a 64 MHz prescaled clock running at 16 MHz

3.12

General purpose inputs/outputs (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without

pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB0 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid

spurious writing to the I/Os registers.

3.13

Direct memory access (DMA)

The DMA is used in order to provide high-speed data transfer between peripherals and memory as well as

memory-to-memory. Data can be quickly moved by DMA without any CPU actions. In this manner, CPU resources

are free for other operations.

The DMA controller has eight channels in total. Each has an arbiter to handle the priority among DMA requests.

DMA main features are:

•

Eight independently configurable channels (requests)

•

Each of the eight channels is connected to dedicated hardware DMA requests, software trigger is also

supported on each channel. This configuration is done by software

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Priorities among requests from channels of DMA are software programmable (four levels consisting of very

high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, and so on)

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Independent source and destination transfer size (byte, half word, word), emulating packing and

unpacking. Source/destination addresses must be aligned on the data size

•

Support for circular buffer management

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Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed

together in a single interrupt request for each channel

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Memory-to-memory transfer (RAM only)

•

Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers

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Access to SRAMs and APB1 peripherals as source and destination

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Programmable number of data to be transferred: up to 65536

3.14

Nested vectored interrupt controller (NVIC)

The interrupts are handled by the Cortex®-M0+ nested vector interrupt controller (NVIC). NVIC controls specific

Cortex®-M0+ interrupts as well as the STM3WB09xE peripheral interrupts.

The NVIC benefits are the following:

•

Nested vectored interrupt controller that is an integral part of the Arm® Cortex®-M0+

•

Tightly coupled interrupt controller provides low interrupt latency

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Control system exceptions and peripheral interrupts

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NVIC supports 32 vectored interrupts

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Four programmable interrupt priority levels with hardware priority level masking

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Software interrupt generation using the Arm® exceptions SVCall and PendSV

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Support for NMI

•

Arm® Cortex® M0+ vector table offset register VTOR implemented

NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

STM32WB09xE

Functional overview

DS14210 - Rev 6

page 18/73

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