PSD813F1 datasheet(67/120 Pages) STMICROELECTRONICS

67 / 120 page

Preliminary

PSD813F1-A

The

PSD813F1

Functional

Blocks

(cont.)

9.4.6 Port C – Functionality and Structure

Port C can be configured to perform one or more of the following functions (see Figure 28):

t MCU I/O Mode

t CPLD Output – McellBC[7:0] outputs can be connected to Port B or Port C.

t CPLD Input – via the Input Micro

⇔Cells

t Address In – Additional high address inputs using the Input Micro

⇔Cells.

t In-System Programming – JTAG port can be enabled for programming/erase of the

PSD813F1 device. (See Section 9.6 for more information on JTAG programming.)

t Open Drain – Port C pins can be configured in Open Drain Mode

t Battery Backup features – PC2 can be configured as a Battery Input (Vstby) pin.

PC4 can be configured as a Battery On Indicator output

pin, indicating when Vcc is less than Vbat.

Port C does not support Address Out mode, and therefore no Control Register is required.

Pin PC7 may be configured as the DBE input in certain microcontroller interfaces.

9.4.7 Port D – Functionality and Structure

Port D has three I/O pins. See Figure 29. This port does not support Address Out mode,

and therefore no Control Register is required. Port D can be configured to perform one or

more of the following functions:

t MCU I/O Mode

t CPLD Output – (external chip select)

t CPLD Input – direct input to CPLD, no Input Micro

⇔Cells

t Slew rate – pins can be set up for fast slew rate

Port D pins can be configured in PSDsoft as input pins for other dedicated functions:

t PD0 – ALE, as address strobe input

t PD1 – CLKIN, as clock input to the Micro

⇔Cells Flip Flops and APD counter

t PD2 – CSI, as active low chip select input. A high input will disable the

Flash/EEPROM/SRAM and CSIOP.

9.4.7.1 External Chip Select

The CPLD also provides three chip select outputs on Port D pins that can be used to

select external devices. Each chip select (ECS0-2) consists of one product term that can be

configured active high or low. The output enable of the pin is controlled by either the output

enable product term or the Direction Register. (See Figure 29.)

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