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PSD813F1 데이터시트(PDF) 73 Page - STMicroelectronics |
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PSD813F1 데이터시트(HTML) 73 Page - STMicroelectronics |
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73 / 120 page ![]() Preliminary PSD813F1-A 69 APD EN PMMR0 BIT 1=1 ALE RESET CSI CLKIN TRANSITION DETECTION EDGE DETECT APD COUNTER POWER DOWN (PDN) DISABLE BUS INTERFACE EEPROM SELECT FLASH SELECT SRAM SELECT PD CLR PD DISABLE FLASH/EEPROM/SRAM PLD SELECT Figure 30. APD Logic Block The PSD813F1 Functional Blocks (cont.) Enable APD Set PMMR0 Bit 1 = 1 PSD in Power Down Mode ALE/AS idle for 15 CLKIN clocks? RESET Yes No OPTIONAL Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 2 through 6. Figure 31. Enable Power Down Flow Chart |
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