PSD813F1 datasheet(28/120 Pages) STMICROELECTRONICS

28 / 120 page

PSD813F1-A

Preliminary

Figure 4. Software Data Protection Disable Flow Chart

9.1.1.6.4 Write OTP Row

Writing to the OTP row (64 bytes) can only be done once per byte, and is enabled by an

instruction. This instruction is composed of three specific Write operations of data bytes at

three specific memory locations followed by the data to be stored in the OTP row (refer to

Table 9). During the write operations, address bit A6 must be zero, while address bits A5-A0

define the OTP Row byte to be written while any EEPROM Sector Select signal (EESi) is

active. Writing the OTP Row is allowed only when SDP mode is not enabled.

9.1.1.7 Programming Flash Memory

Flash memory must be erased prior to being programmed. The MCU may erase Flash

memory all at once or by-sector, but not byte-by-byte. A byte of Flash memory erases to all

logic ones (FF hex), and its bits are programmed to logic zeros. Although erasing Flash

memory occurs on a sector basis, programming Flash memory occurs on a byte basis.

The PSD813F1 main Flash and optional boot Flash require the MCU to send an instruction

to program a byte or perform an erase function (see Table 9). This differs from EEPROM,

which can be programmed with simple MCU bus write operations (unless EEPROM SDP

mode is enabled).

Once the MCU issues a Flash memory program or erase instruction, it must check for the

status of completion. The embedded algorithms that are invoked inside the PSD813F1

support several means to provide status to the MCU. Status may be checked using any of

three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.

WRITE AAh to

Address 555h

WRITE 55h to

Address AAAh

WRITE 80h to

Address 555h

WRITE AAh to

Address 555h

WRITE 55h to

Address AAAh

WRITE 20h to

Address 555h

Page Write

Instruction

Unprotected State

after

tWC (Write Cycle time)

The

PSD813F1

Functional

Blocks

(cont.)

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