H838532H datasheet(125/508 Pages) RENESAS

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Section 5 Power-Down Modes

Rev. 1.00 May 30, 2008 Page 105 of 484

REJ09B0436-0100

5.2.2

Clearing Sleep Mode

Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous counter,

IRQ

4 to IRQ0, WKP7 to WKP0, SCI3-1, SCI3-2, A/D converter, or), or by input at the RES pin.

• Clearing by interrupt

When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.

A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep

(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of

the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the

interrupt enable register.

Interrupt signal and system clock are mutually asynchronous. Synchronization error time in a

maximum is 2/

φ (s).

• Clearing by RES input

When the

RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.

5.2.3

Clock Frequency in Sleep (Medium-Speed) Mode

Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and

MA0 bits in SYSCR1.

5.3

Standby Mode

5.3.1

Transition to Standby Mode

The system goes from active mode to standby mode when a SLEEP instruction is executed while

the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in

TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip

peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of

CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip

RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O

ports go to the high-impedance state.

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