H838532H datasheet(131/508 Pages) RENESAS

131 / 508 page

Section 5 Power-Down Modes

Rev. 1.00 May 30, 2008 Page 111 of 484

REJ09B0436-0100

5.4.4

Notes on External Input Signal Changes before/after Watch Mode

See section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.

5.5

Subsleep Mode

5.5.1

Transition to Subsleep Mode

The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed

while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in

TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D

converter WDT and PWM is halted. As long as a minimum required voltage is applied, the

contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules

are retained. I/O ports keep the same states as before the transition.

5.5.2

Clearing Subsleep Mode

Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, asynchronous

counter, SCI3-2, SCI3-1, IRQ

4 to IRQ0, WKP7 to WKP0) or by a low input at the RES pin.

• Clearing by interrupt

When an interrupt is requested, subsleep mode is cleared and interrupt exception handling

starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is

disabled in the interrupt enable register.

Interrupt signal and system clock are mutually asynchronous. Synchronization error time in a

maximum is 2/

SUB (s).

• Clearing by RES input

Clearing by

RES pin is the same as for standby mode; see Clearing by RES pin in section

5.3.2, Clearing Standby Mode.

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