| 전자부품 데이터시트 검색엔진 |
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H838532H 데이터시트(PDF) 151 Page - Renesas Technology Corp |
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H838532H 데이터시트(HTML) 151 Page - Renesas Technology Corp |
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151 / 508 page ![]() Section 6 ROM Rev. 1.00 May 30, 2008 Page 131 of 484 REJ09B0436-0100 6.3.4 Flash Memory Power Control Register (FLPWCR) Bit Initial value Read/Write 7 PDWND 0 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 0 — 0 — 2 — 0 — 1 — 0 — FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. The power supply circuit can be read in the subactive mode, although it is partly halted in the power-down mode. Bit 7—Power-down Disable (PDWND) This bit selects the power-down mode of the flash memory when a transition to the subactive mode is made. Bit 7 PDWND Description 0 When this bit is 0 and a transition is made to the subactive mode, the flash memory enters the power-down mode. (initial value) 1 When this bit is 1, the flash memory remains in the normal mode even after a transition is made to the subactive mode. Bits 6 to 0—Reserved These bits are always read as 0 and cannot be modified. |
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