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H838532H 데이터시트(PDF) 254 Page - Renesas Technology Corp

부품명 H838532H
상세설명  16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series
PDF  508 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H838532H 데이터시트(HTML) 254 Page - Renesas Technology Corp

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Section 9 Timers
Rev. 1.00 May 30, 2008 Page 234 of 484
REJ09B0436-0100
Bit 1: Timer overflow interrupt enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL
Description
0
TCFL overflow interrupt request is disabled
(initial value)
1
TCFL overflow interrupt request is enabled
Bit 0: Counter clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL
Description
0
TCFL clearing by compare match is disabled
(initial value)
1
TCFL clearing by compare match is enabled
(5) Clock Stop Register 1 (CKSTPR1)
—
TFCKSTP TCCKSTP TACKSTP
S31CKSTP S32CKSTP ADCKSTP TGCKSTP
7
6
543210
1
1111111
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Initial value
Read/Write
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer F is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 2: Timer F module standby mode control (TFCKSTP)
Bit 2 controls setting and clearing of module standby mode for timer F.
TFCKSTP
Description
0
Timer F is set to module standby mode
1
Timer F module standby mode is cleared
(initial value)



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