| 전자부품 데이터시트 검색엔진 |
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H838532H 데이터시트(PDF) 260 Page - Renesas Technology Corp |
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H838532H 데이터시트(HTML) 260 Page - Renesas Technology Corp |
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260 / 508 page ![]() Section 9 Timers Rev. 1.00 May 30, 2008 Page 240 of 484 REJ09B0436-0100 (4) TCF Clear Timing TCF can be cleared by a compare match with OCRF. (5) Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. (6) Compare Match Flag set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value). When TCF matches OCRF, the compare match signal is not generated until the next counter clock. (7) Timer F Operation Modes Timer F operation modes are shown in table 9.10. Table 9.10 Timer F Operation Modes Operation Mode Reset Active Sleep Watch Sub- active Sub- sleep Standby Module Standby TCF Reset Functions Functions Functions/ Halted* Functions/ Halted* Functions/ Halted* Halted Halted OCRF Reset Functions Held Held Functions Held Held Held TCRF Reset Functions Held Held Functions Held Held Held TCSRF Reset Functions Held Held Functions Held Held Held Note: * When φ w/4 is selected as the TCF internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/ φ (s). When the counter is operated in subactive mode, watch mode, or subsleep mode, φ w/4 must be selected as the internal clock. The counter will not operate if any other internal clock is selected. |
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