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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7052 데이터시트(PDF) 389 Page - Renesas Technology Corp |
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SH7052 데이터시트(HTML) 389 Page - Renesas Technology Corp |
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389 / 919 page  363 OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when the next DCNT input clock pulse is input (when underflow occurs). However, when DCNT is H'0000, it remains unchanged at H'0000 no matter how many DCNT input clock pulses are input. When DCNT is cleared by means of the one-shot pulse function, the OSF bit is cleared when the next DCNT input clock is input. The timing in this case is shown in figure 10.40. CK DCNT DCNT input clock Underflow signal Interrupt status flag OSF Interrupt request signal OSI H'0001 H'0000 H'0000 Figure 10.40 OSF Setting Timing in Underflow |
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