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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7052 데이터시트(PDF) 390 Page - Renesas Technology Corp |
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SH7052 데이터시트(HTML) 390 Page - Renesas Technology Corp |
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390 / 919 page  364 Timing of IIF Setting by Interval Timer: When 1 is generated by ANDing the rise of bit 10 to 13 in free-running counter TCNT0L with bit ITVE0 to ITVE3 in the interval interrupt request register (ITVRR), the IIF bit is set to 1 in the timer status register (TSR). The timing in this case is shown in figure 10.41. TCNT0 value N in the figure is the counter value when TCNT0L bit 6 to 13 changes to 1. (For example, N = H'00000400 in the case of bit 10, H'00000800 in the case of bit 11, etc.) CK TCNT0 TCNT input clock Internal interval signal Interrupt status flag IIF Interrupt request signal N – 1 N Figure 10.41 Timing of IIF Setting Timing by Interval Timer |
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