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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SC9RS08KA2 데이터시트(PDF) 24 Page - Freescale Semiconductor, Inc |
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SC9RS08KA2 데이터시트(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 134 page  Chapter 3 Modes of Operation SC9RS08KA2 Series Data Sheet, Rev. 1 24 Freescale Semiconductor the IREFSTEN bit. For the ICS to run in stop, the LVDE and LVDSE bits in the SPMSC1 must both be set before entering stop. 3.6.1 Active BDM Enabled in Stop Mode Entry into active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in the Development Support chapter of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state; it maintains full internal regulation. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After active background mode is entered, all background commands are available. Table 3-3 summarizes the behavior of the MCU in stop when entry into the active background mode is enabled. 3.6.2 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, the voltage regulator remains active. Table 3-4 summarizes the behavior of the MCU in stop when LVD reset is enabled. Table 3-3. BDM Enabled Stop Mode Behavior Mode CPU Digital Peripherals ICS ACMP Regulator I/O Pins RTI Stop Standby Standby On Optionally on On States held Optionally on Table 3-4. LVD Enabled Stop Mode Behavior Mode CPU Digital Peripherals ICS ACMP Regulator I/O Pins RTI Stop Standby Standby Optionally on Optionally on On States held Optionally on |
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