SC9RS08KA2 datasheet(12/134 Pages) FREESCALE

12 / 134 page

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

Section Number

Title

Page

Chapter 9

Internal Clock Source (RS08ICSV1)

9.1

Introduction .....................................................................................................................................75

9.1.1

Features ...........................................................................................................................76

9.1.2

Modes of Operation ........................................................................................................76

9.1.2.1

FLL Engaged Internal (FEI) ...........................................................................76

9.1.2.2

FLL Bypassed Internal (FBI) ..........................................................................76

9.1.2.3

FLL Bypassed Internal Low Power (FBILP) .................................................76

9.1.2.4

Stop (STOP) ....................................................................................................76

9.1.3

Block Diagram ................................................................................................................76

9.2

External Signal Description ............................................................................................................77

9.3

Register Definition ..........................................................................................................................77

9.3.1

ICS Control Register 1 (ICSC1) .....................................................................................77

9.3.2

ICS Control Register 2 (ICSC2) .....................................................................................78

9.3.3

ICS Trim Register (ICSTRM) ........................................................................................79

9.3.4

ICS Status and Control (ICSSC) ....................................................................................79

9.4

Functional Description ....................................................................................................................80

9.4.1

Operational Modes .........................................................................................................80

9.4.1.1

FLL Engaged Internal (FEI) ...........................................................................80

9.4.1.2

FLL Bypassed Internal (FBI) ..........................................................................80

9.4.1.3

FLL Bypassed Internal Low Power (FBILP) .................................................80

9.4.1.4

Stop .................................................................................................................81

9.4.2

Mode Switching ..............................................................................................................81

9.4.3

Bus Frequency Divider ...................................................................................................81

9.4.4

Low Power Bit Usage .....................................................................................................81

9.4.5

Internal Reference Clock ................................................................................................81

9.4.6

Fixed Frequency Clock ...................................................................................................82

Chapter 10

Analog Comparator (RS08ACMPV1)

10.1 Introduction .....................................................................................................................................83

10.1.1 Features ...........................................................................................................................84

10.1.2 Modes of Operation ........................................................................................................84

10.1.2.1 Operation in Wait Mode ..................................................................................84

10.1.2.2 Operation in Stop Mode ..................................................................................84

10.1.2.3 Operation in Active Background Mode ..........................................................84

10.1.3 Block Diagram ................................................................................................................84

10.2 External Signal Description ............................................................................................................86

10.3 Register Definition ..........................................................................................................................86

10.3.1 ACMP Status and Control Register (ACMPSC) ............................................................86

10.4 Functional Description ....................................................................................................................87

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