SC9RS08KA2 datasheet(45/134 Pages) FREESCALE

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SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

Chapter 6

Parallel Input/Output Control

This section explains software controls related to parallel input/output (I/O) and pin control. The

SC9RS08KA2 Series has one parallel I/O port, which includes two I/O pins in the 6-pin package or four

I/O pins in the 8-pin packages, one output-only pin, and one input-only pin. See Chapter 2, “Pins and

Connections,” for more information about pin assignments and external hardware considerations for these

pins.

All of these I/O pins are shared with on-chip peripheral functions as shown in Table 2-1. The peripheral

modules have priority over the I/Os so that when a peripheral is enabled, the I/O functions associated with

the shared pins are disabled. After reset, the shared peripheral functions are disabled so that the pins are

controlled by the I/O. All of the I/Os are configured as inputs (PTADDn = 0) with pullup/pulldown devices

disabled (PTAPEn = 0), except for output-only pin PTA3, which defaults to the BKGD/MS function.

Reading and writing of parallel I/Os is performed through the port data registers. The direction, either input

or output, is controlled through the port data direction registers. The parallel I/O port function for an

individual pin is illustrated in the block diagram shown in Figure 6-1.

Figure 6-1. Parallel I/O Block Diagram

The data direction control bit (PTADDn) determines whether the output buffer for the associated pin is

enabled, and also controls the source for port data register reads. The input buffer for the associated pin is

always enabled unless the pin is enabled as an analog function or is an output-only pin.

Port Read

PTADDn

PTADn

Output Enable

Output Data

Input Data

Synchronizer

Data

BUSCLK

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