SC9RS08KA2 datasheet(46/134 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.

However, the data direction register bit will continue to control the source for reads of the port data register.

When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value

of 0 is read for any port data bit where the bit is an input (PTADDn = 0) and the input buffer is disabled.

In general, whenever a pin is shared with both an alternative digital function and an analog function, the

analog function has priority such that if both the digital and analog functions are enabled, the analog

function controls the pin.

It is a good programming practice to write to the port data register before changing the direction of a port

pin to become an output. This ensures that the pin will not be driven temporarily with an old data value

that happened to be in the port data register.

Associated with the parallel I/O ports is a set of registers located in the high page register space that operate

independently of the parallel I/O registers. These registers are used to control pullup/pulldown and slew

rate for the pins. See Section 6.3, “Pin Control Registers” for more information.

6.1

Pin Behavior in Low-Power Modes

In wait and stop modes, all pin states are maintained because internal logic stays powered up. Upon

recovery, all pin functions are the same as before entering stop.

6.2

Parallel I/O Registers

This section provides information about the registers associated with the parallel I/O ports. The parallel

I/O registers are located within the $001F memory boundary of the memory map, so that short and direct

addressing mode instructions can be used.

Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O. This

section refers to registers and control bits only by their names. A Freescale Semiconductor-provided

equate or header file normally is used to translate these names into the appropriate absolute addresses.

6.2.1

Port A Registers

Port A parallel I/O function is controlled by the data and data direction registers described in this section.

321

PTAD5

PTAD4

PTAD3

PTAD2

PTAD1

PTAD0

Reset:

000

Figure 6-2. Port A Data Register (PTAD)

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