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SC9RS08KA2 데이터시트(PDF) 49 Page - Freescale Semiconductor, Inc |
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SC9RS08KA2 데이터시트(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 134 page ![]() Chapter 6 Parallel Input/Output Control SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 49 76 54 321 0 R 00 PTASE5 PTASE4 PTASE3 0 PTASE1 PTASE0 W Reset: 001 11 011 Figure 6-6. Slew Rate Enable for Port A Register (PTASE) Table 6-5. PTASE Register Field Descriptions Field Description 5:3;1:0 PTASE[5:3;1:0] Output Slew Rate Enable for Port A Bits — Each of these control bits determines whether the output slew rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. |
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