SC9RS08KA2 datasheet(59/134 Pages) FREESCALE

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Chapter 8 Central Processor Unit (RS08CPUV1)

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

8.2.2

Program Counter (PC)

The program counter is a 14-bit register that contains the address of the next instruction or operand to be

fetched.

During normal execution, the program counter automatically increments to the next sequential memory

location each time an instruction or operand is fetched. Jump, branch, and return operations load the

program counter with an address other than that of the next sequential location. This is called a

change-of-flow.

During reset, the program counter is loaded with $3FFD and the program will start execution from this

specific location.

8.2.3

Shadow Program Counter (SPC)

The shadow program counter is a 14-bit register. During a subroutine call using either a JSR or a BSR

instruction, the return address will be saved into the SPC. Upon completion of the subroutine, the RTS

instruction will restore the content of the program counter from the shadow program counter.

During reset, the shadow program counter is loaded with $3FFD.

8.2.4

Condition Code Register (CCR)

The 2-bit condition code register contains two status flags. The content of the CCR in the RS08 is not

directly readable. The CCR bits can be tested using conditional branch instructions such as BCC and BEQ.

These two register bits are directly accessible through the BDC interface. The following paragraphs

provide detailed information about the CCR bits and how they are used. Figure 8-3 identifies the CCR bits

and their bit positions.

Figure 8-3. Condition Code Register (CCR)

The status bits (Z and C) are cleared to 0 after reset.

The two status bits indicate the results of arithmetic and other instructions. Conditional branch instructions

will either branch to a new program location or allow the program to continue to the next instruction after

the branch, depending on the values in the CCR status bit. Conditional branch instructions, such as BCC,

BCS, and BNE, cause a branch depending on the state of a single CCR bit.

Often, the conditional branch immediately follows the instruction that caused the CCR bit(s) to be updated,

as in this sequence:

cmp

;compare accumulator A to 5

blo

lower

;branch if A smaller 5

deca

;do this if A not higher than or same as 5

lower:

CARRY

ZERO

CCR

CONDITION CODE REGISTER

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