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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SC9RS08KA2 데이터시트(PDF) 101 Page - Freescale Semiconductor, Inc |
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SC9RS08KA2 데이터시트(HTML) 101 Page - Freescale Semiconductor, Inc |
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101 / 134 page  Chapter 12 Development Support SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 101 Figure 12-4. BDC Target-to-Host Serial Bit Timing (Logic 1) Figure 12-5 shows the host receiving a logic 0 from the target MCU. Because the host is asynchronous to the target, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level approximately 10 cycles after starting the bit time. HOST SAMPLES BKGD PIN 10 CYCLES BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE PERCEIVED START OF BIT TIME HIGH IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE BKGD PIN R-C RISE 10 CYCLES EARLIEST START OF NEXT BIT |
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