IMX35 datasheet(35/148 Pages) FREESCALE

35 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

NOTE

High is defined as 80% of signal value and low is defined as 20% of signal

value.

Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is

approximately 33 MHz (30 ns). All timings are listed according to this NFC

clock frequency (multiples of NFC clock phases), except NF16 and NF17,

which are not NFC clock related.

4.9.5.2

Wireless External Interface Module (WEIM)

All WEIM output control signals may be asserted and deasserted by internal clocks related to the BCLK

rising edge or falling edge according to the corresponding assertion or negation control fields. The address

always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed

mode according to control register configuration. Output data begins related to BCLK rising edge except

in muxed mode where both rising and falling edge may be used according to control register configuration.

NF5

NF_WP pulse width

tWP

T – 1.5 ns

29.5

NF6

NFALE setup time

tALS

—

NF7

NFALE hold time

tALH

T – 3.0 ns

—

27.5

—

NF8

Data setup time

tDS

—

NF9

Data hold time

tDH

T – 5.0 ns

—

106

—

NF10

Write cycle time

tWC

NF11

NFWE hold time

tWH

T – 2.5 ns

NF12

Ready to NFRE low

tRR

—

8400

—

NF13

NFRE pulse width

tRP

1.5T

—

44.5

—

NF14

READ cycle time

tRC

—

NF15

NFRE high hold time

tREH

0.5T – 2.5 ns

—

NF16

Data setup on READ

tDSR

N/A

—

NF17

Data hold on READ

tDHR

N/A

—

1 The flash clock maximum frequency is 50 MHz.

2 Subject to DPLL jitter specification listed in Table 26, "DPLL Specifications," on page 31.

Table 29. NFC Timing Parameters1 (continued)

Parameter

Symbol

Timing

T = NFC Clock Cycle2

Example Timing for

NFC Clock

≈ 33 MHz

T = 30 ns

Unit

Min.

Max.

Min.

Max.

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