IMX35 datasheet(98/148 Pages) FREESCALE

98 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

4.9.16

1-Wire Timing Specifications

Figure 71 depicts the RPP timing, and Table 60 lists the RPP timing parameters.

Figure 71. Reset and Presence Pulses (RPP) Timing Diagram

MLBCLK high time

tmckh

9.7

9.3

10.6

10.2

—

PLL unlocked

MLBCLK pulse width variation

tmpwv

——

0.7

ns pp

Note2

MLBSIG/MLBDAT input valid

to MLBCLK falling

tdsmcf

1—

—

MLBSIG/MLBDAT input hold

from MLBCLK low

tdhmcf

0—

—

MLBSIG/MLBDAT output high

impedance from MLBCLK low

tmcfdz

0—

tmckl

—

Bus Hold Time

tmdzh

2—

—

Note3

1 The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.

2 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge,

measured in ns peak-to-peak (pp)

3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this

time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.

Table 60. RPP Sequence Delay Comparisons Timing Parameters

Parameters

Symbol

Min.

Typ.

Max.

Units

OW1

Reset time low

tRSTL

480

511

—

µs

OW2

Presence detect high

tPDH

—

µs

OW3

Presence detect low

tPDL

—

240

µs

OW4

Reset time high

tRSTH

480

512

—

µs

Table 59. MLB Device 1024Fs Timing Parameters (continued)

Parameter

Symbol

Min

Typ

Max

Units

Comment

1-Wire bus

DS2502 Tx

“Presence Pulse”

(BATT_LINE)

1-WIRE Tx

“Reset Pulse”

OW1

OW2

OW3

OW4

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