IMX35 datasheet(71/148 Pages) FREESCALE

71 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

Figure 51 depicts the synchronous display interface timing for access level, and Table 52 lists the timing

parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the

DI_DISP3_TIME_CONF Register.

Figure 51. Synchronous Display Interface Timing Diagram—Access Level

IP9

Horizontal blank interval 1

Thbi1

BGXP

× Tdpcp

IP10

Horizontal blank interval 2

Thbi2

(SCREEN_WIDTH – BGXP – FW)

× Tdpcp

IP11

HSYNC delay

Thsd

H_SYNC_DELAY

× Tdpcp

IP12

Screen height

Tsh

(SCREEN_HEIGHT + 1)

× Tsw

IP13

VSYNC width

Tvsw

if V_SYNC_WIDTH_L = 0 than

(V_SYNC_WIDTH + 1)

× Tdpcp

else

(V_SYNC_WIDTH + 1)

× Tsw

IP14

Vertical blank interval 1

Tvbi1

BGYP

× Tsw

IP15

Vertical blank interval 2

Tvbi2

(SCREEN_HEIGHT – BGYP – FH)

× Tsw

1 Display interface clock period immediate value

Display interface clock period average value.

Table 51. Synchronous Display Interface Timing Parameters—Pixel Level (continued)

Parameter

Symbol

Value

Units

Tdicp

HSP_CLK

DISP3_IF_CLK_PER_WR

HSP_CLK_PERIOD

------------------------------------------------------------------

⋅

IP19

DISPB_D3_CLK

DISPB_DATA

IP18

IP20

DISPB_D3_VSYNC

IP17

IP16

DISPB_D3_DRDY

DISPB_D3_HSYNC

other controls

IMX35 데이터시트(PDF) 71 Page - Freescale Semiconductor, Inc

IMX35 데이터시트(HTML) 71 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL