IMX35 datasheet(62/148 Pages) FREESCALE

62 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

4.9.8.3

MII Transmit Signal Timing

The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and

FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of

25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency

must exceed twice the FEC_TX_CLK frequency. Table 45 lists MII transmit channel timings.

1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode.

Figure 41 shows the MII transmit signal timings listed in Table 45.

Figure 41. MII Transmit Signal Timing Diagram

4.9.8.4

MII Asynchronous Inputs Signal Timing

The MII asynchronous timing signals are FEC_CRS and FEC_COL. Table 46 lists MII asynchronous

inputs signal timing.

1 FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

Table 45. MII Transmit Signal Timing

Num

Characteristic1

Min.

Max.

Unit

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER

invalid

5—

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER

valid

—20

FEC_TX_CLK pulse width high

35%

65%

FEC_TX_CLK period

FEC_TX_CLK pulse width low

35%

65%

FEC_TX_CLK period

Table 46. MII Asynch Inputs Signal Timing

Num

Characteristic

Min.

Max.

Unit

M91

FEC_CRS to FEC_COL minimum pulse width

1.5

—

FEC_TX_CLK period

FEC_TX_CLK (input)

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

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