IMX35 datasheet(48/148 Pages) FREESCALE

48 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

NOTE

Test conditions are: pin voltage 1.7 V–1.95 V, capacitance 15 pF for all pins

(both DDR and non-DDR pins), drive strength is high (7.2 mA). “High” is

defined as 80% of signal value and “low” is defined as 20% of signal value.

SDR SDRAM CLK parameters are measured from the 50% point—that is,

“high” is defined as 50% of signal value, and “low” is defined as 50% of

signal value. tCH + tCL will not exceed 7.5 ns for 133 MHz. DDR SDRAM

CLK parameters are measured at the crossing point of SDCLK and SDCLK

(inverted clock).

The timing parameters are similar to the ones used in SDRAM data sheets.

Table 33 indicates SDRAM requirements. All output signals are driven by

the ESDCTL at the negative edge of SDCLK, and the parameters are

measured at maximum memory frequency.

Figure 29. SDRAM Refresh Timing Diagram

Table 34. SDRAM Refresh Timing Parameters

Parameter

Symbol

Min.

Max.

Unit

SD1

SDRAM clock high-level width

tCH

3.4

4.1

SD2

SDRAM clock low-level width

tCL

3.4

4.1

SD3

SDRAM clock cycle time

tCK

7.5

—

SD6

Address setup time

tAS

1.8

—

CAS

RAS

ADDR

ROW/BA

SD6

SD7

SD11

SD10

SDCLK

SD1

SD2

SDCLK

SD3

IMX35 데이터시트(PDF) 48 Page - Freescale Semiconductor, Inc

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