IMX35 datasheet(144/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

144

Product Documentation

All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx.

Revision History

Table 94 shows the revision history of this document.

Table 94. i.MX35 Data Sheet Revision History

Revision

Number

Date

Substantive Change(s)

10/21/2009 • Added information for silicon rev. 2.1

• Updated Table 1, “Ordering Information.”

• Added Table 91, “Silicon Revision 2.1 Signal Ball Map Locations.”

• Added Table 93, “Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch.”

08/06/2009 • Added a line for TA = –40 to 85

oC in Table 13, “I/O Pin DC Electrical Characteristics”

• Filled in TBDs in Table 13.

• Revised Figure 15 and Table 30 by removing FCE = 0 and FCE = 1. Added footnote 3 to the table.

• Added Table 24, “AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive

(1.8 V).”

04/30/2009 • Added Section 4.4, “Reset Timing.”

•In Section 4.8.2, “AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and SDRAM

Modes),” removed Slow Slew rate tables, relabeled Table 22, “AC Electrical Characteristics of DDR

Type IO Pins in mDDR Mode,” and Table 23, “AC Electrical Characteristics of DDR Type IO Pins in

SDRAM Mode,” to exclude mention of slew rate.

•In Section 4.9.5.2, “Wireless External Interface Module (WEIM),” modified Figure 16, “Synchronous

Memory Timing Diagram for Read Access—WSC = 1,” through Figure 21, “Muxed A/D Mode Timing

Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7.”

•In Section 4.9.6, “Enhanced Serial Audio Interface (ESAI) Timing Specifications,” modified

Figure 37, “ESAI Transmitter Timing,” and Figure 38, “ESAI Receiver Timing,” to remove extraneous

signals. Removed a note from Figure 37, “ESAI Transmitter Timing.”

03/2009

• In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6.

02/2009

• Added the following parts to Table 1, “Ordering Information”: PCIMX357CVM5B,

MCIMX353CVM5B, MCIMX353DVM5B, MCIMX357CVM5B, and MCIMX357DVM5B. Throughout

consumer data sheet: Removed or updated information related to Media Local Bus

interface.Updated Section 4.3.1, “Powering Up.”

• Updated values in Table 9, “i.MX35 Power Modes.”

12/2008

• Updated Section 4.3.1, “Powering Up.”

• Section 4.7, “Module-Level AC Electrical Specifications”: Updated NFC, SDRAM and mDDR

SDRAM timing. Inserted DDR2 SDRAM timing.

10/2008

Initial public release

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