AT90SCR100 datasheet(67/433 Pages) ATMEL

67 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

10.1.1

Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

10.1.2

MCUCR – MCU Control Register

• Bit 7..2 – Different bits

These bits are used by other functions of the AVR core, or are reserved bits.

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash

memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot

Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-

mined by the BOOTSZ Fuses. Refer to the section “Memory Programming” on page 377 for

details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must

be followed to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by

hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable

interrupts, as explained in the IVSEL description above. See Code Example below.

Bit

6543210

0x35 (0x55)

JTD

PUD

IVSEL

IVCE

MCUCR

Read/write

R/W

Initial value

0x00

If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02

is programmed, interrupts are disabled while executing from the Application sec-

tion. If Interrupt Vectors are placed in the Application section and Boot Lock bit

BLB12 is programed, interrupts are disabled while executing from the Boot Loader

section. Refer to the section “Memory Programming” on page 377 for details on

Boot Lock bits.

Note

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