AT90SCR100 datasheet(31/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

Clock System

7.1

Overview

The Clock system of AT90SCR100 is based on a 8Mhz Oscillator which feeds a Phase Lock

Loop (PLL) providing a 96Mhz clock frequency. Then, dividers permit to calibrate the frequen-

cies available for the different Peripherals, Core and Memories.

All of the clocks do not need to be active at a given time. In order to reduce power consumption,

the clocks to modules not being used can be stopped by using different sleep modes, as

described in “Power Management and Sleep Modes” on page 43. The clock systems are

detailed below.

Figure 7-1 presents the principal clock systems in the AT90SCR100 and their distribution.

Figure 7-1.

Clock Distribution

Core Divider

Internal RC Oscillator

HS SPI Divider

XTAL1

XTAL2

clk

XTAL

clk

XTAL

clk

PLL

clk

MUX

XTAL

Glitches free

(default)

96Mhz

48Mhz

(by 1, 4, 5, 6, 8, 12, 24, 48, 96)

(by 4, 5, 6, 8, 12, 24, 48, 96)

(Divider by 1

Only for Clk

)

clk

CPU

clk

Flash

clk

Write_Flash

(1)

(2)

clk

Core

clk

I/O

clk

HSSPI

PLL

Clock

PLL

Multi-

-plexer

CPU Core

Flash & Eeprom

IOx

(1): IOx includes: SPI, USART, TWI, AES, Keyboard peripherals

(2): Tn indicates: Timer0, Timer1 and Timer2. Only Timer2 can count using clk

IOx Clock

Controller

High Speed SPI

Block

SCI Divider

(by 8, 12, 16, 20, 24, 48, ...)

clk

PRR1.PRHSSPI

PRR1.PRSCI

PRR1.PRUSB

PRR1.PRSCUSB

SCI

Smart Card

Interface Block

x 1/2

clk

USB

USB Host Controller

(default)

PRR0.PR (IOx)

clk

ASY

Tn Clock

Controller

(default)

PRR0.PR (Tx)

TOSC1

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