AT90SCR100 datasheet(36/433 Pages) ATMEL

36 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% are

required, ensure that the MCU is kept in Reset during the changes.

7.2.4

PLL Clock

The AT90SCR100’s PLL is used to generate internal high frequency clock synchronized by an

external low-frequency clock of 8Mhz desribed in section “Clock Sources” on page 33.

The PLL block combines Phase Frequency Comparator and Lock Detector. This block makes

the comparison between a reference clock and a reverse clock and generates some pulses on

the Up or Down signal depending on the edges of the reverse clock.

Enabling the PLL by setting PLLCR.ON bit starts the stabilization process. As soon as the PLL is

locked, which means that the clock generated is stable, supporting a duty cycle of 50%, the

PLLCR.LOCK bit is set.

When the PLL is locked, it is now possible to switch the PLL Clock Multiplexer to the PLL clock,

by setting the PLLCR.PLLMUX bit. See “PLLCR – Phase Lock Loop (PLL) Control Register” on

page 40.

It is highly recommended that the clkCPU dividers are changed before switching to the clkPLL.

Table 7-4.

Start-up Times for the External Clock Selection

Power Conditions

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (VCC = 5.0V)

SUT1..0

BOD enabled

6 CK

14CK

Fast rising power

6 CK

14CK + 4.1 ms

Slowly rising power

6 CK

14CK + 65 ms

Reserved

The System Clock Prescaler can be used to implement run-time changes of the

internal clock frequency while still ensuring stable operation. Refer to “CLKPR –

Clock Prescale Register” on page 40 for details.

Note

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